Today's computer systems are becoming increasingly sophisticated, permitting users to perform an ever increasing variety of computing tasks at faster and faster rates. The size of the memory and the speed at which it can be accessed bear heavily upon the overall speed of the computer system.
Generally, the principle underlying the storage of data in magnetic media (main or mass storage) is the ability to change and/or reverse the relative orientation of the magnetization of a storage data bit (i.e. the logic state of a “0” or a “1”). The coercivity of a material is the level of demagnetizing force that must be applied to a magnetic particle to reduce and/or reverse the magnetization of the particle. Generally speaking, the smaller the magnetic particle, the higher it's coercivity.
A prior art magnetic memory cell may be a tunneling magneto-resistance memory cell (TMR), a giant magneto-resistance memory cell (GMR), or a colossal magneto-resistance memory cell (CMR). These types of magnetic memory are commonly referred to as magnetic tunnel junction memory (MTJ). FIGS. 1A and 1B provide a perspective view of a typical prior art magnetic memory cell having two conductors. As shown in prior art FIGS. 1A and 1B, a magnetic tunnel junction memory 100 generally includes a data layer 101 (also called a storage layer or bit layer), a reference layer 103, and an intermediate layer 105 between the data layer 101 and the reference layer 103. The data layer 101, the reference layer 103, and the intermediate layer 105 can be made from one or more layers of material. Electrical current and magnetic fields may be provided to the MTJ 100 by an electrically conductive row conductor 107 and an electrically conductive column conductor 109. Often the row and column conductors are substantially transverse.
The data layer 101 is usually a layer of magnetic material that stores a bit of data as an orientation of magnetization M2 that may be altered in response to the application of an external magnetic field or fields. More specifically, the orientation of magnetization M2 of the data layer 101 representing the logic state can be rotated (switched) from a first orientation, representing a logic state of “0”, to a second orientation, representing a logic state of “1”, and/or vice versa.
The reference layer 103 is usually a layer of magnetic material in which an orientation of magnetization M1 is “pinned”, as in fixed, in a predetermined direction. The direction is predetermined and established by microelectronic processing steps employed in the fabrication of the magnetic memory cell.
The data layer 101 and reference layer 103 may be thought of as stacked bar magnets, each long on the X axis 111 and short on the Y axis 113. The magnetization of each layer has a strong preference to align along the easy axis, generally the long X axis 111. The short Y axis 113 is generally the hard axis. As with traditional bar magnets, the data layer and reference layer each have magnetic poles, one at either end of the easy axis. The lines of magnetic force that surround the data layer and reference layers are three-dimensional and flow from the North to the South pole.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer 101 and the reference layer 103. For example, when an electrical potential bias is applied across the data layer 101 and the reference layer 103 in an MTJ 100, electrons migrate between the data layer 101 and the reference layer 103 through the intermediate layer 105. The intermediate layer 105 is typically a thin dielectric layer commonly referred to as a tunnel barrier layer. The phenomena that cause the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling or spin tunneling.
Continuing with the model of an elemental bar magnet, the magnetization of the data layer 101 is free to rotate, but has a strong preference to align in either direction along the easy axis 111 of the data layer 101. The reference layer 103 likewise is aligned along the easy axis 111 but is pinned in a fixed alignment such that it does not freely rotate. The logic state may be determined by measuring the resistance of the memory cell. For example, if the overall orientation of the magnetization in the data layer 101 is parallel to the pinned orientation of magnetization in the reference layer 103 the magnetic memory cell will be in a state of low resistance. If the overall orientation of the magnetization in the data layer 101 is anti-parallel (opposite) to the pinned orientation of magnetization in the reference layer 103, the magnetic memory cell will be in a state of high resistance.
In an ideal setting, the orientation of the alterable magnetic field in the data layer 101 would be either parallel or anti-parallel with respect to the field of the reference layer 103. As both the data layer 101 and the reference layer 103 are generally made from ferromagnetic materials and are positioned in close permanent proximity to each other, the generally stronger reference layer 103 may affect the orientation of the data layer 101. More specifically, the magnetization of the reference layer 103 may generate a demagnetization field that extends from the reference layer 103 into the data layer 101.
The result of this demagnetization field from the reference layer 103 is an offset in the coercive switching field. This offset can result in asymmetry in the switching characteristics of the bit: the amount of switching field needed to switch the bit from parallel to anti-parallel state is different from the amount of switching field needed to switch the bit from anti-parallel state to parallel state. To achieve reliable switching characteristics and to simplify the read/write circuitry, it is desirable to reduce this offset to as near zero as possible.
The magneto-resistance ΔR/R may be described as akin to a signal-to-noise ratio S/N. A higher S/N results in a stronger signal that can be sensed to determine the state of the bit in the data layer. Thus, at least one disadvantage of a tunnel junction memory cell having a pinned reference layer in close and fixed proximity to the data layer is a potential reduction in the magneto-resistance ΔR/R resulting from the angular displacement.
To pin the reference layer during manufacturing, the reference layer must be heated to an elevated temperature in an annealing step. The annealing step typically takes time, perhaps an hour or more. As the reference layer is but one part of the memory being produced, the entire memory is typically subjected to temperatures ranging from about 200 to 300 degrees centigrade while under the influence of a constant and focused magnetic field. Such manufacturing stresses may cause the reference layer to become un-pinned and lose its set orientation if the memory is later subjected to high temperatures. In addition, the characteristics of the data layer may be unknowingly affected by heat during some manufacturing processes.
Although effective, the process of reading the stored bit is somewhat undesirable. In general, the row 107 and column 109 for a given MTJ 100 are selected, a sense current is applied and the resistance is measured and recorded as the initial condition. Next, a larger write current is applied to put the data layer 101 into a known orientation. Then, a sense current is re-applied and the resistance is measured again. The value determined from a known orientation is then compared with the value from the initial condition. The values will either be the same or different, permitting a determination of the data value. If necessary, such as where the initial position is determined to be opposite to the known orientation, a write back can be performed to restore the original initial value. This process is known as double sampling—the first sample being the initial read and the second being after the known orientation write.
Multiple variations of redundant sampling may be performed with double sampling; however, the underlying negative aspect remains unchanged—to determine the value stored in the data layer 101, it is necessary to change the value in the data layer 101. Such change introduces a significant element of risk in data corruption should an error occur during the repetitive sense and write operations.
Although sense operations are less demanding and taxing upon the MTJ 100, the physical design of the MTJ 100 is typically dictated by the stresses imposed by the write process, as both the sense and write operations are performed using the same row and column conductors 107 and 109. As the write magnetic field is typically generated by current applied to the row 107 and column 109 conductors, which are in electrical contact with the MTJ 100, it is desirable for the MTJ 100 to be robust enough to withstand the applied current. Design and manufacturing issues are therefore generally focused upon the requirements imposed by the write operation, such as greater electrical current and magnetic fields, higher applied voltages, more robust characteristics in the power supply, row 107 and column 109 conductors and appropriate buffering spaces.
With respect to magnetic memory components, it is well known that as size decreases, coercivity increases. A large coercivity is generally undesirable, as it requires a greater magnetic field to be switched, which in turn requires a greater power source and potentially larger switching transistors. Providing large power sources and large switching transistors is generally at odds with the focus of nanotechnology to reduce the necessary size of components. In addition, to mitigate the potential of inadvertently switching a neighboring memory cell, nanometer scaled memory cells are generally more widely spaced relative to their overall size than are larger, non-nanometer sized memory cells. Moreover, as the size of the magnetic memory decreases, the unused space between individual memory cells tends to increase.
Moreover, in a typical MRAM array, a significant amount of overall space may be used simply to provide a physical buffer between the cells. Eliminating this buffering space, or otherwise reducing its ratio, may provide a greater volume of storage in the same physical space.
These issues of read vs. write currents, robustness of conductors and power supplies, reduction in size increasing coercivity and a correspondingly greater magnetic field, and current design of the magnetic memory cells also carry over into the design and use of magnetic field sensors. Magnetic field sensors are commonly used in hard drive read cells and read heads. In such implementation, the data layer 101 is termed a sense layer and is oriented by the magnetic field emanating from a storage bit proximate to the read head.
Hence, there is a need for an ultra-high density magnetic memory which overcomes one or more of the drawbacks identified above. The present invention accomplishes this objective, among others.